Fabrication method of semiconductor integrated circuit device and mask

ABSTRACT

A fabrication method of a semiconductor integrated circuit device, comprises preparing a mask having, on a first main surface of a mask substrate, a first light transmitting region, a second light transmitting region disposed at the periphery of the first light transmitting region and permitting inversion of the phase of a light transmitted through the second light transmitting region relative to a light transmitted through the first light transmitting region, and a light shielding region disposed at the periphery of the second light transmitting region; and transferring a predetermined pattern to a photoresist film over the main surface of a wafer through said mask by a projection exposure reduction treatment, wherein said second light transmitting region is formed from a first film deposited over the first main surface of the mask substrate, said light shielding region is formed by a second film deposited over the first main surface of the mask substrate via said first film, and at least one of said first film and second film is formed from a resist film. According to the present invention, the manufacturing time of an edge-enhanced phase shift mask can be reduced.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a fabrication method of a semiconductor integrated circuit device and a mask making technique, particularly to a technique effective when adapted to an exposure technique using a phase shift mask.

[0002] An edge-enhanced phase shift mask is one of phase shift masks. It has, on the main surface of a mask substrate transparent relative to an exposure light, a light shielding film made of a metal film such as chromium, a light transmitting region formed by making an opening in a portion of the light shielding film, and a transparent phase shifter, at the periphery of the light transmitting region (at the edge portion in the vicinity of the boundary with the light shielding film), for inverting the phase of a transmitted light through the light transmitting region by 180°. In the edge-enhanced phase shift mask, by optimizing the edge width according to the transmittance of the edge portion, it is possible to attain an almost similar level of resolving performance improving effect at any transmittance.

[0003] With regards to the edge-enhanced phase shift mask, disclosed in Japanese Unexamined Patent Publication No. Hei 11 (1999)-65083 is, for example, a technique for transferring hole patterns onto a semiconductor wafer by using a photomask which has mask hole patterns having a maximum transmittance, medium transmittance patterns, at the periphery thereof, causing a light which has transmitted through the mask hole patterns to have a phase difference of 180°±60°, and patterns formed at the periphery of the medium transmittance patterns and having the minimum transmittance. In Japanese Unexamined Patent Publication No. Hei 11 (1999)-125894, disclosed is a technique for transferring patterns of a desired size onto a semiconductor wafer by using a photomask having some transparent regions whose mask patterns are made larger than a predetermined size, a semitransparent region disposed at the periphery of each of the transparent regions, having a predetermined width and forming a reverse phase relative to a light transmitted through the transparent region, and a light shielding region disposed at the periphery of the semitransparent region. In Japanese Unexamined Patent Publication No. Hei 10 (1998)-326009, disclosed is a pattern transferring technique through a phase shift mask which has phase shift patterns, at the periphery of each of a plurality of main light transmitting regions, having a low transmittance than that of the main light transmitting regions, wherein the width of some phase shift matters which particularly require edge enhancement, among these phase shift patterns, is made greater than that of the other ones.

SUMMARY OF THE INVENTION

[0004] The present inventor has found that the above-described edge-enhanced phase shift mask techniques are however accompanied with the below-described problems.

[0005] A phase shift mask needs much time for preparation compared with a normal photo mask because formation of a phase shift prolongs its manufacturing step, which leads to the problem that development or fabrication of a semiconductor device using this mask takes much time.

[0006] An object of the present invention is to provide a technique which can shorten the manufacturing time of an edge-enhanced phase shift mask.

[0007] Another object of the present invention is to provide a technique to shorten the fabrication time of a semiconductor integrated circuit device using an edge-enhanced phase shift mask.

[0008] The above-described objects, the other objects and novel features of the present invention will be apparent from the description herein and accompanying drawings.

[0009] Outlines of the representative inventions, among the inventions disclosed by the present application, will next be described briefly.

[0010] In one aspect of the present invention, there is thus provided an edge enhanced phase shift mask having a light shielding body or both of a light shielding body and a phase shifter made of a resist film.

[0011] In another aspect of the present invention, there is thus provided a process having an exposure step for transferring a predetermined pattern to a photosensitive resin film on a wafer by using an edge enhanced phase shift mask having a light shielding body or both of a light shielding body and a phase shifter made of a resist film.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 is a fragmentary plain view of a phase shift mask to be used in the fabrication step of a semiconductor integrated circuit device according to Embodiment 1;

[0013]FIG. 2 is a cross-sectional view taken along a line X1-X1 of FIG. 1;

[0014]FIG. 3 is a graph illustrating the resolving performance improving effect of the phase shift mask of FIG. 1 compared with that of a halftone phase shift mask;

[0015]FIG. 4 is a fragmentary plain view of a phase shift mask in the case where there occurs an misalignment between the first light transmitting region and the second light transmitting region at the outer periphery of the first light transmitting region in the phase shift mask of FIG. 1;

[0016]FIG. 5 is a graph illustrating a change in hole size in the case where there occurs an misalignment between the first light transmitting region and the second light transmitting region at the outer periphery of the first light transmitting region in the phase shift mask of FIG. 1;

[0017]FIG. 6 is a graph showing the evaluation results of a side peak transfer margin caused by the misalignment of the second light transmitting region in the phase shift mask of FIG. 1;

[0018]FIG. 7 is a fragmentary plain view of a self-align system edge-enhanced phase shift resist mask manufactured using the wet etching method investigated by the present inventors;

[0019]FIG. 8 is a cross-sectional view taken along a line X2-X2 of FIG. 7;

[0020]FIG. 9 is a graph showing the evaluation results of the influence of variations in an edge region width in the self-align system edge-enhanced phase shift resist mask of FIG. 7 or 8;

[0021]FIG. 10 is a fragmentary plain view of the mark region of the phase shift mask of FIG. 1;

[0022]FIG. 11 is a cross-sectional view taken along a line X3-X3 of FIG. 10;

[0023]FIG. 12 is a fragmentary plain view of another example of the mark region of the phase shift mask of FIG. 1;

[0024]FIG. 13 is a cross-sectional view taken along a line X4-X4 of FIG. 12;

[0025]FIG. 14 is a fragmentary plain view of a further example of the mark region of the phase shift mask of FIG. 1;

[0026]FIG. 15 is a cross-sectional view taken along a line X5-X5 of FIG. 14;

[0027]FIG. 16 is a fragmentary plain view of a still further example of the mark region of the phase shift mask of FIG. 1;

[0028]FIG. 17 is a cross-sectional view taken along a line X6-X6 of FIG. 16;

[0029]FIG. 18 is a fragmentary plain view of a still further example of the mark region of the phase shift mask of FIG. 1;

[0030]FIG. 19 is a cross-sectional view taken along a line X7-X7 of FIG. 18;

[0031]FIG. 20 is a fragmentary plain view of a still further example of the mark region of the phase shift mask of FIG. 1;

[0032]FIG. 21 is a cross-sectional view taken along a line X8-X8 of FIG. 20;

[0033]FIG. 22 is a fragmentary cross-sectional view during manufacture of the phase shift mask of FIG. 1;

[0034]FIG. 23 is a fragmentary cross-sectional view during manufacture of the phase shift mask following FIG. 22;

[0035]FIG. 24 is a fragmentary cross-sectional view during manufacture of the phase shift mask following FIG. 23:

[0036]FIG. 25 is a schematic explanatory view of the state of exposure treatment using the phase shift mask of FIG. 1;

[0037]FIG. 26 is a fragmentary cross-sectional view of one example of a semiconductor integrated circuit device, during manufacture, according to one embodiment of the present invention;

[0038]FIG. 27 is a fragmentary plain view of a semiconductor integrated circuit device according to another embodiment of the present invention;

[0039]FIG. 28 is a cross-sectional view taken along a line X9-X9 of FIG. 27;

[0040]FIG. 29 is a fragmentary plain view of a phase shift mask to be used in the fabrication step of the semiconductor integrated circuit device of FIG. 27 or FIG. 28; and

[0041]FIG. 30 is a cross-sectional view taken along a line X10-X10 of FIG. 29.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0042] Prior to description of the inventions according to the present application in details, the meanings of the terms used herein will be explained below.

[0043] 1. The term “device surface” means the main surface of a wafer on which device patterns corresponding to a plurality of chip regions are to be formed by photolithography.

[0044] 2. The term “wafer” means a silicon single crystal substrate (semiconductor wafer or a semiconductor integrated circuit wafer; substantially flat circular shape), a sapphire substrate, glass substrate or another insulating, non-insulating or semiconductor substrate, or a composite substrate thereof, each used for the fabrication of a semiconductor integrated circuit device.

[0045] 3. Mask: a generic name of substrates on which patterns of the final size have been drawn. It embraces a “reticle” for forming patterns several times as large as those of the final size. It is used when an exposure equipment using a visible light, ultraviolet light or the like is used. The mask embraces normal mask, resist mask and phase shift mask.

[0046] 4. Normal mask (metal mask or chromium mask): an ordinarily used mask having, on a transparent mask substrate, mask patterns formed of light shielding patterns made of a metal and light transmitting patterns.

[0047] 5. Resist mask: The term “resist mask” as used herein means that obtained by exposing a film composed mainly of a photosensitive resist to energy beam lithography or photo lithography using an electron beam (ion beam) or light (ultraviolet light such as vacuum ultraviolet light, far ultraviolet light or near ultraviolet light, or visible light), thereby patterning on a mask substrate. As a light shielding film, it blocks all or part of ultraviolet rays such as vacuum ultraviolet ray, far ultraviolet ray and near ultraviolet ray, and visible light. Photosensitivity is an attribute of the above-described resin itself (if necessary, a light absorber or light scattering substance may be added) . An emulsion mask or the like in which an additive composition such as silver halide plays a main role in photosensitivity is, in principle, outside the definition of the “resist mask” in the present invention. In other words, the “resist mask” does not exhibit desired light shielding property for the first time by development, but has already had light shielding property before development or at the time when applied on a mask substrate. It is needless to say that inclusion of various additives including such a composition is not prohibited. The resist is usually composed mainly of an organic resin, but addition of an inorganic substance is permitted.

[0048] In the field of a semiconductor, ultraviolet rays are classified as follows: A ray having a wavelength less than 400 nm but about 50 nm or greater is called “ultraviolet ray”, that having a wavelength of 300 nm or greater is called “near ultraviolet ray”, that having a wavelength less than 300 nm but 200 nm or greater is called “far ultraviolet ray”, and that having a wavelength less than 200 nm is called “vacuum ultraviolet ray”. Examples in this application are described mainly in a vacuum ultraviolet ray region having a wavelength less than 200 nm, but it is needless to say that the present invention can be applied to a far ultraviolet region, by a KrF excimer laser, having a wavelength less than 250 nm but 200 nm or greater, if modification as described later in Examples is conducted. It is also possible to apply the principle of the present invention even to a short wavelength edge region of ultraviolet rays having a wavelength less than 100 nm but 50 nm or greater and a visible short wavelength edge region of about 400 nm to about 500 nm.

[0049] 6. Halftone phase shift mask: a kind of a phase shift mask having a halftone film which serves as both a shifter and a light shielding film and has a transmittance of 1% or greater but less than 40%, and a halftone shifter whose phase shift amount relative to that of a portion having no halftone film inverts a phase of light.

[0050] 7. Edge enhanced phase shift mask: a kind of a phase shift mask which has a shifter disposed at the peripheral profile portion of a light transmitting region for transferring patterns.

[0051] 8. The term “light shielding (light shielding region, light shielding film or light shielding pattern” means that it has optical characteristics permitting transmittance of less than 40% of an exposure light radiated on the region. Generally, one permitting transmittance of from several % to less than 30% is used. Particularly in a binary mask (or binary light shielding pattern) used as a substitute for the conventional chromium mask, the transmittance of the light shielding region is almost 0, that is, less than 1%, desirably less than 0.5%, more practically less than 0.1%. The term “transparent (transparent film or transparent region)”, on the other hand, means that is has optical characteristics permitting transmittance of 60% or greater of a light irradiated on the region. The transmittance of the transparent region is almost 100%, that is, 90% or greater, desirably 99% or greater.

[0052] 9. The term “metal” in the context of a mask light shielding material means chromium, chromium oxide or a similar metal compound, in a broad sense, a metal-containing single substance, compound or composite having a light shielding action.

[0053] 10. The term “resist film” means a film which is usually composed mainly of an organic solvent, a base resin and a photosensitive agent and also contains another component. By an exposure light such as ultraviolet ray or electron beam, the photosensitive agent causes a photochemical reaction and a product of the photochemical reaction or this product of the photochemical reaction as a catalyst causes a large change in a dissolution rate of the base resin in a development solution, whereby patterns are formed by exposure and development subsequent thereto. When a dissolution rate of a base resin in a development solution at an exposure portion increases, such a resist is called “posi type resist”, while a dissolution rate of a base resin in a development solution at an exposure portion decreases, such a resist is called “nega type resist”. In general, a resist film does not contain an inorganic material in its main component, but an Si-containing resist film is exceptionally embraced in this resist film.

[0054] A general difference between a resist film and a photosensitive SOG (Spin On Glass) resides in that the photosensitive SOG contains, in a main component, Si—O or Si—N and this portion is made of an inorganic material. The main skeleton of the photosensitive SOG is SiO₂. Whether it is inorganic or organic is determined by that it has CH₃ or the like bonded at the terminal point thereof or not. In general, the photosensitive SOG is stable and widely used when having an organic terminal. But, either organic or inorganic is usable

[0055] 11. In the field of a semiconductor, ultraviolet rays are classified as follows: A ray having a wavelength less than 400 nm but 50 nm or greater is called “ultraviolet ray”, that having a wavelength of 300 nm or greater is called “near ultraviolet ray”, that having a wavelength less than 300 nm but 200 nm or greater is called “far ultraviolet ray”, and that having a wavelength less than 200 nm is called “vacuum ultraviolet ray”. Examples in this application are described mainly in a vacuum ultraviolet ray region having a wavelength less than 200 nm, but it is needless to say that the present invention can be applied to a far ultraviolet region, by a KrF excimer laser, having a wavelength less than 250 nm but 200 nm or greater, if modification as described later in Examples is conducted. It is also possible to apply the principle of the present invention to a short wavelength end region of ultraviolet rays having a wavelength less than 100 nm but 50 nm or greater.

[0056] 12. The term “semiconductor integrated circuit device” means not only that formed over a semiconductor or insulating substrate such as silicon wafer or sapphire substrate but also another insulating substrate, for example, glass such as TFT (Thin Film Transistor) or STN (Super Twisted Nematic) liquid crystals unless otherwise specifically indicated.

[0057] 13. Hole pattern: fine pattern such as contact hole or through hole having a two dimensional size equal to or not greater than an exposure wavelength on a wafer. In general, it is square, rectangular near square or pentagonal on a mask, but in many cases is circular on the wafer.

[0058] 14. Line pattern: means a strip pattern constituting an interconnect or the like on a wafer.

[0059] In the below-described embodiments, a description will be made after divided in plural sections or in plural embodiments if necessary for convenience's sake. These plural sections or embodiments are not independent each other, but in a relation such that one is a modification example, details or complementary description of a part or whole of the other one unless otherwise specifically indicated.

[0060] In the below-described examples, when a reference is made to the number of elements (including the number, value, amount and range), the number of elements is not limited to a specific number but can be not greater than or less than the specific number unless otherwise specifically indicated or in the case it is principally apparent that the number is limited to the specific number.

[0061] Moreover in the below-described embodiments, it is needless to say that the constituting elements (including element steps) are not always essential unless otherwise specifically indicated or in the case where it is principally apparent that they are essential.

[0062] Similarly, in the below-described embodiments, when a reference is made to the shape or positional relationship of the constituting elements, that substantially analogous or similar to it is also embraced unless otherwise specifically indicated or in the case where it is utterly different in principle. This also applies to the above-described value and range.

[0063] In all the drawings for describing the below-described embodiments, elements having like function will be identified by like reference numerals and overlapping descriptions will be omitted

[0064] In the drawings used in these embodiments, even a plain view is sometimes hatched to facilitate understanding of the drawing.

[0065] In the below-described embodiments, MIS.FET (Metal Insulator Semiconductor Field Effect Transistor) will be abbreviated as MIS, while a p-channel type MIS.FET and an n-channel type MTS.FET will be abbreviated as pMIS and nMIS, respectively.

[0066] The embodiments of the present invention will hereinafter be described specifically based on accompanying drawings.

[0067] (Embodiment 1)

[0068] In recent years, a variety of low-produced articles such as ASIC (Application Specific IC) and system LSI (Large Scale Integrated circuit) have not used masks so frequently, causing an increase in the ratio of the cost of masks in the cost of a semiconductor integrated circuit device. Particularly in a phase shift mask which needs more preparation steps than the ordinarily-employed mask and moreover, has complex preparation steps, there is increasingly a demand for shortening the preparation time and reducing the cost of the mask.

[0069] According to a resist mask technique for constituting a light shielding body on a mask substrate from a resist mask, shortening of the preparation time and a cost reduction of a mask can be actualized. It is therefore desired to apply this resist mask technique to a halftone phase shift mask which has been used widely because of easy preparation.

[0070] It is necessary, for the preparation of a halftone mask, to simultaneously control the transmittance of an exposure light and a phase stably at high precision, but there remain many problems in the development of a resist material for a halftone phase shift mask, for example, a change in optical constant caused by a change in a light absorber in a resist film for a light shielding body due to irradiation of an exposure light.

[0071] The present inventors therefore investigated a manufacturing method, by utilizing a resist mask technique, of an edge enhanced phase shift mask which method can improve the resolution level to be equal to that of a halftone phase shift mask. A description on the resist mask can be found in Japanese Patent Application No. Hei 11 (1999)-185221 (applied on Jun. 30, 1999), Japanese Patent Application No. 2000-246466 (Aug. 15, 2000) or Japanese Patent Application No. 2000-246506 (Aug. 15, 2000) by the present inventors and the like.

[0072] The edge enhanced phase shift mask can bring about similar-level improving effects of resolving performance at any transmittance by optimizing the width of an edge according to the transmittance of an exposure light at the edge portion. In this Embodiment, therefore, a shifter is formed at the peripheral profile portion of a light transmitting region by using a resist film or photosensitive SOG film which is free of a light absorber, is stable and relatively transparent to irradiation. A resist film for a light shielding body which is employed for a binary mask is used around the portion. This makes it possible to prepare an edge-enhanced phase shift mask from a resist mask instead of a normal mask which use has so far considered.

[0073]FIG. 1 is a fragmentary plain view of an edge enhanced phase shift resist mask RM1 (which will hereinafter be described “mask RM1” simply) used in the fabrication process (exposure treatment) of a semiconductor integrated circuit device of this Embodiment, while FIG. 2 is a cross-sectional view taken along a line X1-X1 of FIG. 1.

[0074] Here, mask RM1 for transferring hole patterns onto a wafer is illustrated. A mask substrate 1 constituting this mask RM1 is made, for example, of a synthetic quartz glass plate which is transparent to an exposure light. It has a first main surface and a second main surface on the back side thereof (reverse side). Over the first main surface of this mask substrate 1, formed is, for example, a first light transmitting region TA1 of a planar square shape. The first light transmitting region TA1 is a transparent region formed by exposing the first main surface of the mask substrate 1. At the peripheral profile portion of this first light transmitting region TA1, a second light transmitting region TA2 in a planar frame form is disposed so as to encompass therewith the light transmitting region TA1 and around the second light transmitting region TA2, a light shielding region SA is disposed.

[0075] The second light transmitting region TA2 is a region functioning as a phase shifter and is formed of a phase shift film (first film) 2 on the first main surface of the mask substrate 1. This phase shift film 2 is made of, for example, the above-described resist film or photosensitive SOG film. The thickness d of the phase shift film 2 can be expressed by d=λ/(2(n−1)) (wherein λ means the wavelength of an exposure light and n stands for a refractive index at the exposure wavelength of the phase shift film 2) and it is, for example, about 200 nm±6 nm. As the resist material for forming the phase shift film 2, following resist materials can be given as examples. As the resist material when an exposure light upon transferring patterns to a wafer is an i line (λ=365 nm), a novolak resin resist is usable. When the exposure light is KrF ((λ=248 nm), a polyhydroxystyrene resin resist is usable as the resist material. When the exposure light is ArF (λ=193 nm), an ArF resist such as polymethyl methacrylate (PMMA) or alternating (COMA) type is usable. When the exposure light is F₂ (λ=157 nm), a fluorine-containing resin resist or ladder silicone is usable as the resist material.

[0076] The transmittance of an exposure light in the above-described second light transmitting region TA2 is set, for example at 3% to 100%, 20 to 90% or 50 to 90%, preferably 50%, 60%, 80% or 100%. In this Embodiment 1, it is set at a value between the transmittance of an exposure light in the first light transmitting region TA1 and that in the light shielding region SA. By optimizing the width of this second light transmitting region TA2, a substantially stable resolving performance improving effect can be attained without depending on the transmittance of an exposure light through a material constituting the second light transmitting region TA2. Upon formation of the second light transmitting region TA2 from a resist film, it is possible to narrow a light absorbing portion, which has low resistance against irradiation of an exposure light in a resist film, as much as possible and heighten the transmittance of the exposure light, making it possible to use a material stable against irradiation of an exposure light. In other words, a resist film can be selected more freely. For example, when the thickness of a resist film for the formation of the second light transmitting region TA2 is set at 0.3 μm and the transmittance of an exposure light is 10% or greater, the stability against irradiation of an exposure light can be improved greatly.

[0077] In the mask RM1 of this Embodiment, the transmittance of an exposure light and phase in the second light transmitting region TA2 can simultaneously be controlled stably. By the present technique, the thickness of the resist film for the formation of the second light transmitting region TA2 can be controlled at accuracy of ±3% or less and phase control can also be controlled with high precision. In general, at least the phase must be controlled within 180°±10° in order to improve resolving performance by the phase shift effect and the phase of the second light transmitting region TA2 can be controlled with such precision depending on the present technique. As a result, a phase shift resist mask capable of actualizing improvement, thereby having a similar resolving power to that of a halftone phase shift mask can be prepared.

[0078] The light shielding region SA is formed by a light shielding film (second film) 3 deposited over the phase shift film 2. In this light shielding film 3, an opening of a planar square shape having a center common with the first light transmitting region TA1 is formed so as to expose the first light transmitting region TA1 and the phase shift film 2 at the peripheral profile portion thereof. The light shielding film 3 has a thickness of, for example, about 0.4 μm. As the resist material for forming the light shielding film 3, following resist materials can be given as examples. As the resist material when an exposure light upon transferring patterns to a wafer is an i line (λ=365 nm), a novolak resin resist containing 2-hydroxychalcone as a light absorber is usable. When the exposure light is KrF ((λ=248 nm), a novolak resin resist containing anthracenemethanol as a light absorber is usable as the resist material. When the exposure light is ArF (λ=193 nm) or F₂ (λ=157 nm), a polyhydroxystyrene resin resist or novolak resin resist is usable as the resist material.

[0079] For the formation of the phase shift film 2 and the light shielding film 3 from a resist film, either a posi type or nega type resist film may be used in consideration of their characteristics. A posi type resist film is however preferred from the viewpoint of preparation of a mask. When a posi type resist film is used for transferring patterns by an electron beam or the like, only a portion to which hole patterns are to be transferred may be exposed to an electron beam, in short, a relatively small area must be drawn so that drawing time by an electron beam can be reduced much compared with the use of a nega type resist film. In FIG. 2, “A” represents a size corresponding to the length of one side of the first light transmitting region TA1, while “B” represents a size corresponding to the length of one side of a square opening portion formed by the first light transmitting region TA1 and the second light transmitting region TA2.

[0080]FIG. 3 is a graph showing the resolving performance improving effect of mask RM1 compared with the resolving performance of a halftone phase shift mask. In this graph, a mask bias is determined on the assumption that hole patterns, for example, of 180 to 200 nm are transferred onto a wafer. Calculation results of light intensity distribution “Edge” while setting the size A at about 260 nm, the size B at about 400 to 440 nm and the transmittance of the second light transmitting region TA2 at about 80% are shown in this graph, together with light intensity distribution “HT” by a popularly used halftone phase shift mask having a transmittance of about 6%. Exposure conditions employed here were: KrF (λ=248 nm) as an exposure light, numerical aperture of projection lens NA=0.68 and coherence σ=0.50 (which will hereinafter be called “first exposure conditions) . In FIG. 3, F means focus, more specifically, F=0 means best focus and F=4 means 0.4 μm defocus. For example, when the size B is 420 nm, light intensity distribution is almost similar to the light intensity distribution HT of 6% halftone phase shift mask at either best focus or 0.4 μm defocus.

[0081] In this Embodiment 1, drawing is conducted twice for the preparation of the mask RM1 as will be described later so that there is fear that misalignment during twice drawing has an adverse effect. FIG. 4 is a fragmentary plain view of the mask RM1 when there occurs offset between the first light transmitting region TA1 and the second light transmitting region TA2 at the peripheral profile portion of TA1. The transmittance of an exposure light through the second light transmitting region TA2 is, for example, about 80%. The size A is, for example, about 260 nm and size B about 420 nm. FIG. 5 illustrates the hole size when in the mask RM1 of this Embodiment 1, misalignment between the first light transmitting region TA1 and the second light transmitting region TA2 which is the peripheral profile portion of TA1 both in the direction X (horizontal direction in FIG. 4) and in the direction Y (perpendicular direction in FIG. 4) becomes, for example, about 40, 80, or 120 nm (the size on a phase shift resist mask, which is presumed to be greater by 4 times so it corresponds to 10, 20 or 30 nm on a wafer). If the allowance of a change in the hole size due to the misalignment is, for example, about 5 nm, offset of about 80 nm can be permitted even if defocus of 0.3 μm is taken into consideration. There is a fear that the size peak value becomes higher on the side where the second light transmitting region TA2 becomes wider due to offset, causing a decrease in the size peak transfer margin. Evaluation results of it are shown in FIG. 6. Ith means the threshold value of a subpeak strength. This threshold value Ith is, for example, 0.298. When the threshold value exceeds it, the subpeak is transferred onto a resist film on a wafer. It is apparent from FIG. 6 that there exists a sufficient margin for side peak transfer when the offset is <100 nm in terms of the size on a mask. Exposure conditions are, for example, similar to the above-described first exposure conditions. The alignment precision of the present electron beam drawing apparatus is about 100 nm so that the above-described alignment precision can be easily attained.

[0082] In FIGS. 7 and 8, shown, for comparison, are a fragmentary plain view of a self-align system edge-enhanced phase shift resist mask 50 formed using wet etching method investigated by the present inventors and a cross-sectional view taken along a line X2-X2 of FIG. 7.

[0083] Over the first main surface of a mask substrate 51 of this edge-enhanced phase shift resist mask 50, a phase shift film 53 is deposited via a light shielding film 52. The light shielding film 52 is made of a water soluble organic light shielding film, while the phase shift film 53 is made of a resist film. In the light shielding film 52, an opening 54 of a planar square shape is made so as to expose the first main surface of the mask substrate 1. The size B of the opening portion 54 is, for example, about 380 to 460 nm. In the phase shift film 53, a first light transmitting region TA51 of a planar square shape having a center common with the opening portion 54 and smaller than the opening portion 54 is opened. The size of this first light transmitting region TA51 is, for example, about 260 nm. A planarly overlapping portion of the phase shift film 53 with the opening portion 54 at the peripheral profile portion of this first light transmitting region TA51 is a second light transmitting region TA52. In this technique, upon formation of the opening portion by removal of a portion of the phase shift film 53 deposited over the first main surface of the mask substrate 51 by photolithography, the water soluble light shielding film 52 is removed simultaneously. The light shielding film 52 exposed from the side surface portion of this opening portion is dissolved in the transverse direction, thereby forming a pentroof structure with the phase sift film 53. No misalignment between the first light transmitting region TA51 and the second light transmitting region TA52 therefore does not occur, but it is difficult to control the edges on the side surfaces of the opening portion 54 of the light shielding film 52. In FIG. 9, shown are evaluation results of the influence of a change in the edge region width in the self-align system edge-enhanced phase shift resist mask 50 in FIG. 7 and FIG. 8. It shows the relationship between the focus and hole size when the size B is changed. If a change in the hole size due to a change in the width of the edge region is suppressed to 5 nm or less at a defocus amount set at not greater than 0.3 μm, the edge region width must be controlled to 420±10 nm in terms of a size on a wafer. Assuming that a mask has patterns 4 times larger than they are on the final product, control precision of the edge position within ±40 nm in terms of a size on a mask is necessary. Exposure conditions here are similar to the first exposure conditions. If the thickness of the resist film on the mask is not greater than 0.3 μm, it seems to be very difficult to control the precision of the edge position within ±40 nm by wet etching. The above-described self align system edge-enhanced phase shift resist mask technique is disclosed by the present inventors in Japanese Patent Application No. 2000-278665 (applied on Sep. 8, 2000).

[0084] A predetermined mark such as alignment mark formed on the mask RM1 will next be described with reference to FIGS. 10 to 21. FIGS. 10 to 15 illustrate the case where the resist film over the mask substrate 1 is a posi type resist film, while FIGS. 16 to 21 illustrate the case where the resist film over the mask substrate 1 is a nega type resist film.

[0085]FIG. 10 is a fragmentary plain view of a mark region of mask RM1, and FIG. 11 is a cross-sectional view taken along a line X3-X3 of FIG. 10. Over the first main surface of the mask substrate 1, a light shielding film 3 is deposited via a phase shift film 2. A portion of the light shielding film 3 is opened to expose the underlying phase shift film 2, whereby a third light transmitting region TA3 is formed. This third light transmitting region TA3 is a pattern for the formation of the mark. The third light transmitting region TA3 is covered all over with the phase shift film 2 and within this third light transmitting region TA3, inversion of the phase of a transmitted light does not occur. The transmittance of an exposure light through the third light transmitting region TA3 is equal to that through the second light transmitting region TA2.

[0086]FIG. 12 is a fragmentary plain view illustrating another example of a mark region of mask RM1, and FIG. 13 is a cross-sectional view taken along a line X4-X4 of FIG. 12. Over the first main surface of the mask substrate 1, for example, a fourth light transmitting region TA4 of a planar strip shape is formed. This fourth light transmitting region TA4 is a transparent region formed by exposing the first main surface of the mask substrate 1. The light transmittance of an exposure light through this region is equal to that through the first light transmitting region TA1. At the peripheral profile portion of this fourth light transmitting region TA4, a fifth light transmitting region TA5 is disposed and outside of this fifth light transmitting region TA5, a light shielding region SA is disposed. The fifth light transmitting region TA5 is made of a phase shift film 2 and the transmittance and phase of the exposure light is similar to those of the second light transmitting region TA2. The fourth light transmitting region TA4 and firth light transmitting region TA5 are patterns for forming the above-described mark.

[0087]FIG. 14 is a fragmentary plain view illustrating a further example of the mark region of mask RM1, and FIG. 15 is a cross-sectional view taken along a line X5-X5 of FIG. 14. Over the first main surface of the mask substrate 1, for example, a sixth light transmitting region TA6 of a planar strip shape is formed. This sixth light transmitting region TA6 is a transparent region formed by exposing the first main surface of the mask substrate 1 and the transmittance of an exposure light through this region is equal to that through the first light transmitting region TA1. This sixth light transmitting region TA6 is a pattern for forming the above-described mask. Outside of this sixth light transmitting region TA6, a light shielding region SA is disposed. The surfaces of the phase shift film 2 (its upper surface and side surfaces on the side of the sixth light transmitting region TA6) are covered with the light shielding film 3 so as not to expose the phase shift film 2 on the sixth light transmitting region TA6.

[0088]FIG. 16 is a fragmentary plain view illustrating a still further example of the mark region of mask RM1 and FIG. 17 is a cross-sectional view taken along a line X6-X6 of FIG. 16. The mark structure illustrated in FIG. 16 or 17 is similar to that illustrated in FIG. 10 or 11 except that it is prepared using a nega type resist film. Over the first main surface of the mask substrate 1, a pattern of the light shielding film 3 in the planar strip shape is formed. This pattern of the light shielding film 3 is encompassed by a transparent light transmitting region. Here, the pattern of this light shielding film 3 is a pattern for forming the above-described mark.

[0089]FIG. 18 is a fragmentary plain view illustrating a still further example of the mark region of mask RM1, while FIG. 19 is a cross-sectional view taken along a line X7-X7 of FIG. 18. The mark structure illustrated in FIG. 18 or 19 is similar to that illustrated in FIG. 12 or 13 except that it is prepared using a nega type resist film. Over the first main surface of the mask substrate 1, a pattern of the phase shift film 2 in the planar strip shape is formed. Over the pattern of this phase shift film 2, a pattern of the light shielding film 3 in the planar strip shape a little narrower than the pattern of the phase shift film 2 is formed. In other words, at the peripheral profile portion of the pattern of the light shielding film 3, the phase shift film 2 is disposed and it is then encompassed by a transparent light transmitting region. Here, the patterns of this phase shift film 2 and light shielding film 3 are patterns for forming the above-described mark.

[0090]FIG. 20 is a fragmentary plain view illustrating a still further example of a mark region of mask RM1, and FIG. 21 is a cross-sectional view taken along a line X8-X8 of FIG. 20. The mark structure illustrated in FIG. 20 or 21 is similar to that illustrated in FIG. 14 or 15 except that it is formed using a nega type resist film. Over the first main surface of the mask substrate 1, a pattern of a phase shift film 2 in the planar strip shape is formed. A pattern of a light shielding film 3 of a planar strip shape a little wider than the pattern width of the phase shift film 2 is formed so as to cover the whole surface (upper surface and side surfaces) of the pattern of the phase shift film 2. The light shielding film 3 is encompassed by a transparent light transmitting region. The pattern of the light shielding film 3 is a pattern for forming the above-described mask. In the mark region of the mask RM1, FB drawing time can be shortened or problems such as side peak transfer can be avoided by adopting the structures as illustrated in FIGS. 10 to 21.

[0091] One example of a manufacturing method of the mask RM1 in FIG. 1 will next be described with reference to FIGS. 22 and 23. FIGS. 22 and 23 are fragmentary cross-sectional views during the manufacturing step of mask RM1.

[0092] As illustrated in FIG. 22, a transparent mask substrate 1 having first and second main surfaces are prepared. A posi type resist film is coated over the first main surface to form a phase shift film 2. For the formation of the phase shift film 2, a photosensitive SOG film may be employed instead of the resist film. Then, a pattern is drawn by selectively exposing, to an electron beam EB, a region of the phase shift film 2 on which a first light transmitting region is to be formed. Development is conducted to remove the region which has been exposed to the electron beam EB, whereby a first light emitting region TA1 from which the first main surface of the mask substrate 1 is exposed is formed in the phase shift film 2 as illustrated in FIG. 23.

[0093] As illustrated in FIG. 24, a posi type resist film for the formation of a light shielding film 3 is coated on the first main surface of the mask substrate 1 so as to cover the phase shift film 2 and the exposed surface of the mask substrate 1 through the first light transmitting region TA1. Regions of the light shielding film 3 in which a first light transmitting region and a second light transmitting region are to be formed are then selectively exposed to an electron beam EB to draw a pattern. In order to prevent dissolution of the constituents of the phase shift film 2 in the constituents of the light shielding film 3, it is preferred to add hardening treatment by baking or the like prior to the application of the resist film for the formation of the third light shielding film 3. Development is then conducted to remove the regions exposed to an electron beam EB, whereby the mask RM1 as illustrated in FIG. 1 is manufactured. Prior to the above described twice exposure to an electron beam EB, application of a water soluble conductive organic film may be laid over the phase shift film 2 or light shielding film 3. Examples of the water soluble conductive organic film include “Espacer” (trade name; product of Showa Denko K.K.) and “Aquasave” (trade name; product of Mitsubishi Rayon Company, Limited). During exposure to an electron beam EB, the water soluble conductive organic film is electrically connected with an earth. After exposure to an electron beam EB is completed, the water soluble conductive organic film is removed upon development of the resist film constituting the phase shift film 2 or light shielding film 3. This method makes it possible to prevent charging with an electron beam EB, thereby preventing inconveniences such as abnormality of pattern shape and misalignment of patterns.

[0094] The exposure treatment using the mask RM1 of Embodiment 1 is schematically drawn in FIG. 25.

[0095] A semiconductor substrate (which will hereinafter be called “substrate” simply) 4S of a wafer 4 is made of, for example, silicon (Si) single crystal and on its main surface (surface on which a device is to be formed), predetermined semiconductor circuit elements have been formed. Over the main surface of the substrate 4S, an interlevel insulating film 5 is deposited. The interlevel insulating film 5 is made of, for example, silicon oxide (SiO₂), over which, for example, a posi type photoresist film 6 has been coated.

[0096] Above the main surface of the wafer 4, the mask RM1 is disposed via a projection lens 7 of a projection exposure reduction equipment. The mask RM1 is disposed under the state of free attachment or removal so that the first main surface of the mask RM1 will be directed toward the projection lens 7. Upon exposure, an exposure light L irradiated from the side of the second main surface of the mask RM1 passes through the first main surface of the mask RM1 and is incident on the projection lens 7. By this projection lens 7, projection exposure reduction of the mask pattern of the mask RM1 to the photoresist film 6 of the wafer 4 is conducted. At the mask RM1, 180° phase inversion of a light transmitted through the first light transmitting region TA1 and a light transmitted through the second light transmitting region TA2 occurs. This makes it possible to steepen the rise and break of an edge in the waveform of a light transmitted through the first light transmitting region TA1, thereby improving the resolution degree of a projected pattern. An exposure system may be either step and repeat system or step and scan system.

[0097] Application of the technique of Embodiment 1 to a fabrication process of a semiconductor integrated circuit device having, for example, a CMIS circuit will next be described. FIG. 26 is a fragmentary cross-sectional view during fabrication of a semiconductor integrated circuit device according to Embodiment 2.

[0098] A substrate 4S constituting a wafer 4 is made of, for example, p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm. In the main surface (a surface on which a device is to be formed) of the substrate 4S, an isolation portion of a groove shape (SGI (Shallow Groove Isolation) or STI (Shallow Trench Isolation)) 10 is formed. This isolating portion 10 of a groove shape is formed by embedding, for example, a silicon oxide film (SiO₂) or the like in the groove formed on the main surface of the substrate 4S. On the main surface side of the substrate 4S, a p type well PWL and an n type well NWL are formed. In the p type well PWL, for example, boron is introduced, while in the n-type well NWL, for example, phosphorus is introduced. On active regions of the p type well PWL and n type well NWL surrounded by the isolation portion 2, nMISQn and pMISQp are formed.

[0099] The gate insulating film 11 of each of the nMISQn and pMISQP is made of, for example, a silicon oxide film having a thickness of 6 nm. The thickness of the gate insulating film means the thickness of a film in terms of silicon oxide (which will hereinafter be called “converted film thickness) and it sometimes does not coincide with the actual film thickness. The gate insulating film 11 may be made of a silicon oxynitride film instead of a silicon oxide film. In other words, nitrogen is segregated on the interface between the gate insulating film 11 and the substrate 4S. Since a silicon oxynitride film is, compared with a silicon oxide film, highly effective for suppressing generation of an interface level in the film or for reducing electron traps, so that hot carrier resistance of the gate insulating film 11 and also dielectric strength can be improved. Moreover, since the silicon oxynitride film does not easily penetrate therethrough impurities compared with a silicon oxide film, use of it can suppress variations in the threshold voltage due to diffusion of impurities in the gate electrode material on the side of the substrate 4S. For the formation of the silicon oxynitride film, the substrate 4S may be heat treated in a nitrogen-gas-containing atmosphere, for example, NO, NO₂ or NH₃.

[0100] The gate insulating film 11 may be formed of, for example, a silicon nitride film or a composite insulating film of a silicon oxide film and a silicon nitride film. If the gate insulating film 11 made of a silicon oxide film is thinned to less than 5 nm thick, particularly less than 3 nm thick in the above-described converted film thickness, lowering of dielectric breakdown owing to occurrence of a direct tunnel current or hot carrier due to stress becomes apparent. A silicon nitride film has a higher dielectric constant than a silicon oxide film so that its converted film thickness becomes thinner than the actual film thickness. In other words, even if a silicon nitride film is physically thick, its capacity is similar to that of a relatively thin silicon oxide film. By constituting the gate insulating film 11 from a single silicon nitride film or a composite film thereof with a silicon oxide film, the effective film thickness can be increased compared with that of the gate insulating film made of a silicon oxide film, making it possible to alleviate lowering in dielectric breakdown caused by occurrence of a direct tunnel current or hot carrier due to stress.

[0101] The gate electrode 12 of each of nMISQn and pMISQp is formed by stacking, for example, a titanium silicide (TiSi_(x)) layer or cobalt silicide (CoSi_(x)) layer over a low resistance polycrystalline silicon film. The structure of the gate electrode 12 is not limited to it. Alternatively, it may be a so-called polymetal gate structure formed of a laminate film of, for example, a low resistance polycrystalline silicon film, WN (tungsten nitride) film and a W (tungsten) film. On the side surface of the gate electrode 12, side walls 12 are formed of, for example, silicon oxide.

[0102] Semiconductor regions 14 for a source and drain of nMISQn have an n⁻ type semiconductor region adjacent to a channel and an n⁺ type semiconductor region which is connected to the n⁻ type semiconductor region and disposed apart from the channel by a space corresponding to the n⁻ type semiconductor region. To the n⁻ type semiconductor region and n⁺ type semiconductor region, for example, phosphorus or arsenic has been introduced. On the other hand, semiconductor regions 15 for a source and drain of pMISQp have a p⁻ type semiconductor region adjacent to a channel and a p⁺ type semiconductor region which is connected to the p⁻ type semiconductor region and disposed apart from the channel by a space corresponding to the p⁻ type semiconductor region. To the p⁻ type semiconductor region and p⁺ type semiconductor region, for example, boron has been introduced. All over the upper surface of these semiconductor regions 14, 15, a silicide layer such as titanium silicide or cobalt silicide layer is formed.

[0103] Over such a substrate 4S, an interlevel insulating film 5 a is deposited. This interlevel insulating film 5 a is made of a film having a high reflow property which can be embedded in a narrow space between gate electrodes 12, 12, for example, BPSG (Boron-doped Phospho Silicate Glass) film. Alternatively, it may be made of an SOG (Spin On Glass) film formed by spin coating. In the interlevel insulating film 5 a, fine plural contact holes (hole patterns) CNT are formed. From the bottom of each of the contact holes CNT, a portion of the upper surface of each of the semiconductor regions 14, 15 is exposed. Upon formation (exposure) of these contact holes CNT, the above-described mask RM1 (refer to FIG. 1) is used. These contact holes are formed, for example, in the following manner. After deposition of an interlevel insulating film 5 a by CVD (Chemical Vapor Deposition), a posi type photoresist film, for example, is formed thereover by coating. As illustrated in FIG. 25, patterns of the mask RM1 are transferred to a photoresist film on the wafer by projection exposure reduction treatment as illustrated in FIG. 25, followed by a series of photolithography steps such as development, whereby photoresist patterns are formed. With these photoresist patterns as etching masks, the interlevel insulating film exposed therefrom is removed, whereby contact holes CNT are formed. In each of these contact holes CNT, a plug 16 is formed. The plug 16 is formed, for example, by depositing a titanium nitride (TiN) film and a tungsten (W) film by CVD over the interlevel insulating film 5 a including the inside of the contact hole CNT, removing unnecessary portions of the titanium nitride film and tungsten film over the interlevel insulating film 5 a by etch back and leaving these films only in the contact holes CNT. Over the interlevel insulating film 5 a, a first-level interconnect 17 made of, for example, tungsten is formed. The first-level interconnect 17 is electrically connected with the semiconductor regions 14, 15 for source-drain of nMISQn and pMISQP and gate electrode 12 via the plug 16.

[0104] According to this Embodiment 1, the following advantages are available.

[0105] (1) An etching step for the formation of the light shielding film 3 from a metal film becomes unnecessary by constituting the phase shift film 2 and light shielding film 3 of the mask RM1 from a resist film. Production of a phase shift mask which otherwise needs more steps, in the number and complexity, than those for a normal mask can be simplified, making it possible to greatly shorten the manufacturing time of the mask RM1 having high resolution characteristics.

[0106] (2) An etching step necessary for the formation of the light shielding film 3 from a metal film becomes unnecessary by constituting the phase shift film 2 and light shielding film 3 of the mask RM1 from a resist film. Production of a phase shift mask which otherwise needs more steps, in the number and complexity, than those for a normal mask can be simplified, making it possible to greatly reduce the manufacturing cost of the mask RM1 having high resolution characteristics.

[0107] (3) An etching step necessary for the formation of the light shielding film 3 from a metal film becomes unnecessary by constituting the light shielding film 3 of the mask RM1 from a resist film. Size error due to etching can therefore be eliminated, whereby pattern size accuracy of the mask RM1 having high resolution characteristics can be improved.

[0108] (4) A considerable reduction in the production time of the mask RM1 leads to a drastic decrease in the fabrication (including development and manufacture) time of a semiconductor integrated circuit device using it.

[0109] (5) A considerable reduction in the production cost of the mask RM1 leads to a drastic decrease in the cost of a semiconductor integrated circuit device fabricated using it.

[0110] (6) Owing to an improvement in the pattern size accuracy on the mask RM1, the size accuracy of the patterns to be transferred onto a wafer can be improved.

[0111] (7) The advantage as described in (6) brings about an improvement in the performance of a semiconductor integrated circuit device.

[0112] (8) By the advantage as described above in (6), miniaturization of a semiconductor integrated circuit device can be promoted.

[0113] (Embodiment 2)

[0114] In this Embodiment 2, described is a case where a hole-pattern-dense region and a hole-pattern-sparse region exist in the same layer.

[0115]FIG. 27 is a fragmentary plain view of a semiconductor integrated circuit device having a logic circuit portion according to Embodiment 2; and FIG. 28 is a cross-sectional view taken along a line X9-X9 of FIG. 27. In FIG. 27, a through hole (hole pattern) TH is drawn in a planar square shape, but it is actually circular.

[0116] Over an interlevel insulating film 5 a, an interlevel insulating film 5 b made of, for example, silicon oxide is deposited. Over the interlevel insulating film 5 b, an interlevel insulating film 5 c made of, for example, silicon oxide is deposited via a thin insulating film 20 a made of silicon nitride (Si₃N₄ or the like) of about 5 nm thick. In the insulating film 20 a and interlevel insulating film 5 c, interconnect trenches 21 are formed. In these interconnect trenches 21, second-level inlaid interconnects 22 are formed. Each of the second inlaid interconnects 22 has a main conductor film made of, for example, copper (Cu) and a thin barrier conductive film made of titanium nitride (TiN) which is formed to encompass the circumference (bottom surface and side surfaces) of the main conductor film. Over the interlevel insulating film 5 c, an interlevel insulating film 5 d made of, for example, silicon oxide is deposited via a thin insulating film 20 b made of, for example, silicon nitride of about 5 nm thick. These interlevel insulating film 5 d and insulating film 20 b, a plurality of through holes TH are formed. From the bottom of each of the through holes TH, a portion of the second-level inlaid interconnect 22 is exposed. The drawing suggests that there exist, in the same layer, a region in which through holes are disposed densely (a hole pattern dense region, the left side of FIG. 27 or FIG. 28) and a region in which through holes TH are disposed sparsely (a hole pattern sparse region, the right side of FIG. 27 or FIG. 28).

[0117]FIG. 29 is a fragmentary plain view of an edge-enhanced enhanced phase shift resist mask RM2 (which will hereinafter be called “mask RM2”, simply) to be used for transfer of the patterns of a through hole TH illustrated in FIG. 27 and FIG. 28; and FIG. 30 is a cross-sectional view taken along a line X10-X10 of FIG. 29.

[0118] For example, in a semiconductor integrated circuit device having a logic circuit portion, a hole pattern dense region and a hole pattern sparse region usually exist in the same layer. Under the conditions when σ is as large as 0.6 to 0.7, imbalance as described below sometimes occurs: the side peak transfer margin is small in spite that the focus margin is large in the hole pattern dense region, while the side peak transfer margin is large in spite that the focus margin is small in the hole pattern sparse region.

[0119] In the edge enhanced phase shift resist mask, according to the investigation by the present inventors, there is a tendency that when the edge region (corresponding to the second light transmitting region TA2) is widened, an increase in the focus margin but a reduction in the side peak transfer margin occur, while when the edge region is narrowed, a reduction in the focus margin but an increase in the side peak transfer margin occur.

[0120] As illustrated in FIG. 29 and FIG. 30, the edge region (corresponding to the second light transmitting region TA2) is narrowed in the hole pattern dense region, while the edge region is widened in the hole pattern sparse region. This heightens a total focus margin, thereby enabling to enlarge a total side peak transfer margin. Thus, by changing the width of the edge region depending on how patterns are disposed, the process margin can be heightened.

[0121] In the above-described Embodiment 1 and the present Embodiment 2, formation of hole patterns was described. What was described can be applied not only to the hole patterns but also to line patterns (for example, patterns for the above-described first-level interconnect 17 or interconnect trench 21) or another complex pattern. In such a case, process margin can be expanded by changing the edge region width according to the patterns.

[0122] The present invention by the present inventors was so far described specifically based on Embodiments. It is needless to say that the present invention is not limited to the above-described Embodiments, but can be changed within an extent not departing from the gist of the invention.

[0123] In the above-described Embodiments, use, as a semiconductor integrated circuit substrate, of a semiconductor substrate made of a single semiconductor was described, but the semiconductor integrated circuit substrate is not limited thereto, but an SOI (Silicon On Insulator) substrate having a thin semiconductor layer disposed over an insulating layer or an epitaxial substrate having an epitaxial layer formed over a semiconductor substrate may be used.

[0124] In the above-described embodiments, KrF was used as a main exposure light, but not only it, but also i line (wavelength: 365 nm), ArF (wavelength: 193 nm) or F₂ (wavelength: 157 nm) can be used as an exposure light.

[0125] Described above was application of the present invention, made by the present inventor, to a fabrication method of a semiconductor integrated circuit device having a CMIS circuit for which the invention has been completed. The present invention can be applied not only to the above-described method but also to a fabrication method of a semiconductor integrated circuit device having a memory circuit such as DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory) or a flash memory (EEPROM; Electric Erasable Programmable Read Only Memory), a fabrication method of a semiconductor integrated circuit device having a logic circuit such as micro processor unit, and a fabrication method of an embedded type semiconductor integrated circuit device having both the memory circuit and logic circuit on the same semiconductor substrate. The present invention is also effective when adapted to the production of superconductive apparatus, micromachine, magnetic head, electronic device and liquid-crystal panel.

[0126] Advantages available from the representative inventions, among inventions disclosed by the present application, will next be described briefly.

[0127] (1) It becomes possible to shorten the manufacturing time of an edge-enhanced phase shift mask by constituting only a light shielding body of an edge-enhanced phase shift mask or both of the shielding body and a phase shifter from a resist film.

[0128] (2) It becomes possible to shorten the production time of a semiconductor integrated circuit device using an edge-enhanced phase shift mask, by imparting the invention with an exposure step for transferring a predetermined pattern to a photosensitive resin film on a wafer through the edge-enhanced phase shift mask having only a light shielding body or both of the light shielding body and a phase shifter constituted from a resist film. 

What is claimed is:
 1. A fabrication method of a semiconductor integrated circuit device, comprising the steps of: preparing a mask having, on a first main surface of a mask substrate, a first light transmitting region, a second light transmitting region disposed at the periphery of the first light transmitting region and permitting inversion of the phase of a light transmitted through the second light transmitting region relative to a light transmitted through the first light transmitting region, and a light shielding region disposed at the periphery of the second light transmitting region; and transferring predetermined patterns to a photoresist film over the main surface of a wafer by projection exposure reduction treatment using the mask, wherein said second light transmitting region is formed from a first film deposited over the first main surface of the mask substrate, wherein said light shielding region is formed from a second film deposited over the first main surface of the mask substrate via said first film, and wherein at least one of said first film and second film is formed from a resist film.
 2. A method according to claim 1, wherein said predetermined patterns are each a hole pattern or a line pattern.
 3. A method according to claim 1, wherein an exposure light used upon said projection exposure reduction treatment is KrF having a wavelength of 248 nm.
 4. A method according to claim 1, wherein the transmittance of the exposure light through said second light transmitting region is an intermediate value between that through said first light transmitting region and that through said light shielding region.
 5. A method according to claim 1, wherein the transmittance of the exposure light through said second light transmitting region ranges from 3% to 100%.
 6. A method according to claim 1, wherein the transmittance of the exposure light through said second light transmitting region ranges from 20% to 90%.
 7. A method according to claim 1, wherein the transmittance of the exposure light through said second light transmitting region ranges from 50% to 90%.
 8. A method according to claim 1, wherein in said mask, said second light transmitting region has a width made smaller in a densely-disposed region of said predetermined patterns than in a sparsely-disposed region of said predetermined patterns.
 9. A fabrication method of a semiconductor integrated circuit device, comprising the steps of: preparing a mask having, on a first main surface of a mask substrate, a first light transmitting region, a second light transmitting region disposed at the periphery of the first light transmitting region and permitting inversion of the phase of a light transmitted through the second light transmitting region relative to a light transmitted through the first light transmitting region, and a light shielding region disposed at the periphery of the second light transmitting region; and transferring predetermined patterns to a photoresist film over the main surface of a wafer by projection exposure reduction treatment using said mask, wherein said second light transmitting region is formed from a first film deposited over the first main surface of the mask substrate, wherein said light shielding region is formed from a second film deposited over the first main surface of the mask substrate via said first film, wherein said first film is formed from a photosensitive SOG film, and wherein said second film is formed from a resist film.
 10. A method according to claim 9, wherein said predetermined patterns are each a hole pattern or a line pattern.
 11. A method according to claim 9, wherein an exposure light used upon said projection exposure reduction treatment is KrF having a wavelength of 248 nm.
 12. A method according to claim 9, wherein the transmittance of the exposure light through said second light transmitting region is an intermediate value between that through said first light transmitting region and that through said light shielding region.
 13. A method according to claim 9, wherein the transmittance of the exposure light through said second light transmitting region ranges from 3% to 100%.
 14. A method according to claim 9, wherein the transmittance of the exposure light through said second light transmitting region ranges from 20% to 90%.
 15. A method according to claim 9, wherein the transmittance of the exposure light through said second light transmitting region ranges from 50% to 90%.
 16. A method according to claim 9, wherein in said mask, said second light transmitting region has a width made smaller in a densely-disposed region of said predetermined patterns than in a sparsely-disposed region of said predetermined patterns.
 17. A fabrication method of a semiconductor integrated circuit device, comprising the steps of: preparing a mask having, on a first main surface of a mask substrate, a first light transmitting region, a second light transmitting region disposed at the periphery of the first light transmitting region and permitting inversion of the phase of a light transmitted through the second light transmitting region relative to a light transmitted through the first light transmitting region, and a light shielding region disposed at the periphery of the second light transmitting region; and transferring predetermined patterns to a photoresist film over the main surface of a wafer by projection exposure reduction treatment using said mask, wherein said second light transmitting region is formed from a first film deposited over the first main surface of the mask substrate, wherein said light shielding region is formed from a second film deposited over the first main surface of the mask substrate via said first film, and wherein said first film and said second film are each formed from a resist film.
 18. A method according to claim 17, wherein said predetermined patterns are each a hole pattern or a line pattern.
 19. A method according to claim 17, wherein an exposure light used upon said projection exposure reduction treatment is KrF having a wavelength of 248 nm.
 20. A method according to claim 17, wherein the transmittance of the exposure light through said second light transmitting region is an intermediate value between that through said first light transmitting region and that through said light shielding region.
 21. A method according to claim 17, wherein the transmittance of the exposure light through said second light transmitting region ranges from 3% to 100%.
 22. A method according to claim 17, wherein the transmittance of the exposure light through said second light transmitting region ranges from 20% to 90%.
 23. A method according to claim 17, wherein the transmittance of the exposure light through said second light transmitting region ranges from 50% to 90%.
 24. A method according to claim 17, wherein in said mask, said second light transmitting region has a width made smaller in a densely-disposed region of said predetermined patterns than in a sparsely-disposed region of said predetermined patterns.
 25. A mask comprising, on a first main surface of a mask substrate, a first light transmitting region, a second light transmitting region disposed at the periphery of the first light transmitting region and permitting inversion of the phase of a light transmitted through the second light transmitting region relative to a light transmitted through the first light transmitting region, and a light shielding region disposed at the periphery of the second light transmitting region, wherein said second light transmitting region is formed from a first film deposited over the first main surface of the mask substrate, wherein said light shielding region is formed from a second film deposited over the first main surface of the mask substrate via said first film, and wherein at least one of said first film or said second film is formed from a resist film.
 26. A mask according to claim 25, wherein the transmittance of the exposure light through said second light transmitting region is an intermediate value between that through said first light transmitting region and that through said light shielding region.
 27. A mask according to claim 25, wherein the transmittance of the exposure light through said second light transmitting region is equal to or lower than that through said first light transmitting region.
 28. A mask according to claim 25, wherein the transmittance of the exposure light through said second light transmitting region ranges from 3% to 100%.
 29. A mask according to claim 25, wherein the transmittance of the exposure light through said second light transmitting region ranges from 20% to 90%.
 30. A mask according to claim 25, wherein the transmittance of the exposure light through said second light transmitting region ranges from 50% to 90%.
 31. A mask according to claim 25, wherein in said mask, said second light transmitting region has a width made smaller in a densely-disposed region of said predetermined patterns than in a sparsely-disposed region of said predetermined patterns.
 32. A mask comprising, on a first main surface of a mask substrate, a first light transmitting region, a second light transmitting region disposed at the periphery of the first light transmitting region and permitting inversion of the phase of a light transmitted through the second light transmitting region relative to a light transmitted through the first light transmitting region, and a light shielding region disposed at the periphery of the second light transmitting region, wherein said second light transmitting region is formed from a first film deposited over the first main surface of the mask substrate, wherein said light shielding region is formed from a second film deposited over the first main surface of the mask substrate via said first film, wherein said first film is formed from a photosensitive SOG film, and wherein said second film is formed from a resist film.
 33. A mask according to claim 32, wherein the transmittance of the exposure light through said second light transmitting region is an intermediate value between that through said first light transmitting region and that through said light shielding region.
 34. A mask according to claim 32, wherein the transmittance of the exposure light through said second light transmitting region is equal to or lower than that through said first light transmitting region.
 35. A mask according to claim 32, wherein the transmittance of the exposure light through said second light transmitting region ranges from 3% to 100%.
 36. A mask according to claim 32, wherein the transmittance of the exposure light through said second light transmitting region ranges from 20% to 90%.
 37. A mask according to claim 32, wherein the transmittance of the exposure light through said second light transmitting region ranges from 50% to 90%.
 38. A mask according to claim 32, wherein in said mask, said second light transmitting region has a width made smaller in a densely-disposed region of said predetermined patterns than in a sparsely-disposed region of said predetermined patterns.
 39. A mask comprising, on a first main surface of a mask substrate, a first light transmitting region, a second light transmitting region disposed at the periphery of the first light transmitting region and permitting inversion of the phase of a light transmitted through the second light transmitting region relative to a light transmitted through the first light transmitting region, and a light shielding region disposed at the periphery of the second light transmitting region, wherein said second light transmitting region is formed from a first film deposited over the first main surface of the mask substrate, wherein said light shielding region is formed from a second film deposited over the first main surface of the mask substrate via said first film, and wherein said first film and said second film are each formed from a resist film.
 40. A mask according to claim 39, wherein the transmittance of the exposure light through said second light transmitting region is an intermediate value between that through said first light transmitting region and that through said light shielding region. 